CpE 690 Introduction to VLSI Design Bryan Ackland Dept. of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ 07030
Note: This is a tentative schedule – please check this page for updates
Week	Dates	Subject	Reading	Homework
1		Course Overview & Syllabus Introduction to VLSI Design	Lecture 0 Lecture 1	HW1: Download and install Evita VHDL from Aldec Chapters 1-4
2		FPGA Design & VHDL – part I: Design Challenges Entities, Architectures & Signals Dataflow Modeling	Lecture 2 Reading Materials: (a) Programmable Logic Design from Xilinx (b) VHDL Cookbook	HW2 Xilinx Download Full Adder Tutorial
3		FPGA Design & VHDL – part II Behavioral Modeling Structural Modeling Subprograms & Overloading	Lecture 3	HW3
4		FPGA Design & VHDL – part III VHDL Synthesis Finite State Machines Test Bench Design	Lecture 4
5		MOS Transistors and CMOS Logic	Lecture 5	HW4
6		CMOS Fabrication and Layout	Lecture 6 Video: “Silicon Run”	HW5 Design Project
7		CMOS Transistor Theory & DC Response	Lecture 7	HW6
8		Delay and Transient Response	Lecture 8
9		Mid-Term Exam
10		Logical Effort and Multi-Stage Logic Network Design	Lecture 9 SPICE	HW 7
11		Combinational Circuit Design Pseudo-NMOS logic Dynamic Logic	Lecture 10
12		Design for Low Power	Lecture 11	HW8
13		Design of Arithmetic Circuits	Lecture 12
14		Final Review
15		Final Exam