Hang Liu @ Stevens Institute of Technology

CPE 517: Computer and Digital Systems Architecture

Personnel:
- Instructor: Hang Liu
- TA: Mingju He (mhe6@stevens.edu)
Syllabus:
- Week 1: Course overview and Introduction
- Week 2: Introduction
- Week 3: Pipeline and ISA
- Week 4: Pipeline and ISA
- Week 5: Individual meeting and feedbacks
- Week 6: Review of memory hierarchy
- Week 7: Memory hierarchy design
- Week 8: Instruction Level Parallelism
- Week 9: Instruction Level Parallelism
- Week 10: Midterm exam (close book)
- Week 11: Data level parallelism
- Week 12: Thread level parallelism
- Week 13: Thread level parallelism
- Week 14: Advanced topics: warehouse-scale computing & GPUs
- Week 15: Final exam (close book)
Course projects:
- Lab 1: Understanding how to translate C into MIPS with MARS
- Lab 2: Understanding MIPS datapath
- Lab 3: Understanding and implementing five-stage pipeline
- Lab 4: Understanding the benefits and overheads of TLP via OpenMP-based Breadth-First Search (BFS)
Software and datasets:
- MARS simulator
- BFS project related converter and datasets
Acknowledgement:
- Dr. Seung Woo Son from University of Massachusetts Lowell