CPE 487 Digital System Design Spring 2018 Bryan Ackland Dept. of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ 07030
Note: This is a tentative schedule – please check this page for updates
Week	Dates	Subject	Notes	Homework
1	1/17	Class Organization Overview of Digital System Design	Lecture 0 Lecture 1	HW1: Install Evita_VHDL from Aldec Chapters 1-4
	1/19	Introduction to VHDL	Lecture 2 Lecture 3
2	1/24	Entities, Architectures & Signals	Lecture 4	HW2 Xilinx Download Full Adder Tutorial Xilinx Windows 8-10
	1/26	Dataflow Modeling	Lecture 5
3	1/31	Behavioral Modeling (I)	Lecture 6
	2/2			HW3 Due: HW2
4	2/7	Using Xilinx Toolsets		Lab Assignments
	2/9	Behavioral Modeling (II)	Lecture 7	HW4
5	2/14	No Class
	2/16	Structural Modeling	Lecture 8	Due: HW3
6	2/21	Monday Schedule
	2/23	Lab 1
7	2/28	Generics & Configurations	Lecture 9
	3/2	Lab 2
8	3/7	Midterm Review		Due: HW4
	3/9	Midterm Exam
9	3/14	Spring Recess
	3/16
10	3/21	Midterm Solutions Project		Project MC14510B
	3/23	Lab 3
11	3/28	Subprograms & Overloading	Lecture 10	HW 5
	3/30	Good Friday
12	4/4	Packages & Libraries	Lecture 11
	4/6	Lab 4
13	4/11	VHDL for Synthesis (I)	Lecture 12	Due: HW5
	4/13	Lab 5
14	4/18	VHDL for Synthesis (II)		HW 6
	4/20	Lab 6
15	4/25	Finite State Machines	Lecture 13	Due: Project I
	4/27			HW 7
16	5/2	Test Bench	Lecture 14	Due: HW6
	5/3	Final Review	Synthesis Solution	Due: HW7 Due: Project II
17		Final Exam: Thursday May 10, 9:00 AM – 12:00 Noon, Mclean 104/106/119