EE 471 Transport Phenomena in Solid State Devices Spring 2018 Bryan Ackland Dept.
of Electrical and Computer Engineering Hoboken,
NJ 07030 |
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Note:
This is a tentative schedule – please check this page for updates |
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Week |
Dates |
Subject |
Notes |
Homework |
1 |
1/19 |
Introduction to Solid State Circuits |
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|
2 |
1/23 |
Electrons &
Holes in Semiconductors |
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1/26 |
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3 |
1/30 |
Transport in
Semiconductors |
|
|
2/2 |
Due: HW1 |
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4 |
2/6 |
Generation &
Recombination |
|
|
2/9 |
PN Junction (I) |
|
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5 |
2/13 |
No Class |
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2/16 |
PN Junction (II) |
|
Due HW2 |
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6 |
2/20 |
Optoelectronic
Devices |
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2/23 |
Due HW3 |
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7 |
2/27 |
Midterm Review |
|
Due HW4 |
3/2 |
Midterm Exam |
|
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8 |
3/6 |
Mid-term
Solutions |
|
|
3/9 |
MOS Capacitor
(I) |
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9 |
3/13 |
Spring Recess |
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3/16 |
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10 |
3/20 |
MOS Capacitor
(II) |
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|
3/23 |
MOS Transistor |
|
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11 |
3/27 |
Due HW5 |
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3/30 |
Good Friday |
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12 |
4/3 |
CMOS Digital
Circuits |
Due HW6 |
|
4/6 |
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13 |
4/10 |
SPICE Simulation |
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4/13 |
CMOS Fabrication
& Layout |
|
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14 |
4/17 |
Due HW7 |
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4/20 |
CMOS Delay &
Transient Response |
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15 |
4/24 |
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4/27 |
CMOS Power
Dissipation |
Due HW8 |
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16 |
5/1 |
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5/3 |
Final Review |
|
Due HW9 Due Project |
|
17 |
|
Final Exam: Wednesday May 16, 9:00 AM –
12:00 Noon, Peirce 116/120 |